Three nanometers.
That is the gate pitch gap between Samsung's new 3D-stacked transistor and the one Intel showed at the same conference. In the sub-2nm logic era, three nanometers is a generation.
At the 2026 VLSI Symposium in Hawaii, Samsung Electronics demonstrated a vertically stacked FET with a 42nm gate pitch—the industry's smallest—and won Best Paper. The paper scored 8.29 out of 10 among more than 1,000 submissions, according to TechTimes. This is not an incremental node shrink. Samsung has moved the transistor from planar geometry to a three-dimensional stack, placing NMOS and PMOS on top of each other. The result is a complementary FET (CFET) that crams twice the logic into the same footprint.
The density roadmap just acquired a new axis. Samsung owns the steepest vector on it.
Intel Had a CFET. Samsung's Was Smaller.
The gate pitch—the lateral spacing between transistor gates—is the fundamental ruler of logic scaling. Samsung drove it down to 42 nanometers. The previous best was 48 nanometers. At the same conference, Intel demonstrated a CFET inverter at a 45-nanometer gate pitch. A credible effort. Suddenly second place.
Samsung's paper, titled "First Demonstration of 3D Stacked FETs at Gate Pitch of 42nm Featuring Triple-Stacked Nanosheet Channels for Advanced Logic Applications," details an architecture that stacks three nanosheet channels per layer. The wider current flow path boosts drive current. The intermediate insulating layer, developed specifically for this structure, electrically isolates the upper and lower transistors—solving a problem that has bedeviled CFET research for years. The paper was selected as a Technical Highlight, a designation reserved for work the program committee considers field-shifting.
Why This Best Paper Isn't a Press Release
The VLSI Symposium sits alongside IEDM and ISSCC as one of the three most selective conferences in semiconductor engineering. A Best Paper award here is not marketing dressed up as research. It is a room full of the world's most skeptical device physicists voting that your transistor works.
Samsung's 8.29 score came from a program committee that reviewed more than a thousand submissions. The research team—Hwang Dong-hoon, Kwon Wook-hyun, and Jung Young-chae from the Logic TD team at Samsung's Semiconductor R&D Center—presented a working device, not a simulation. "Looking at the development history of many senior researchers, we have broken through area limits through vertical stacked structures," Kwon told BusinessKorea.
The validation matters because CFETs have been a theoretical target for years. Building one that switches at this density, with functional isolation between layers, is the difference between a roadmap slide and a manufacturing trajectory.
The Architecture That Doubles Density
Planar transistors spread across the silicon surface. A CFET builds upward. Samsung's implementation stacks NMOS and PMOS vertically, using three nanosheet channels per layer. The channels are the current-carrying paths. More channels mean more current. Stacking them means the transistor's footprint on the die is cut in half.
The intermediate insulating layer is the critical enabler. Without it, the stacked transistors would interfere electrically, creating leakage paths that destroy power efficiency. Samsung developed a proprietary direct vertical interconnect technology it calls "RBC" to connect the layers without consuming additional lateral space, as reported by BigGo Finance.
The theoretical gain is stark: stacking transistors vertically reduces the area occupied by half, doubling density per unit area. Samsung claims the technology achieves twice the power efficiency and a 100% performance improvement over planar designs, according to the Asia Business Daily. These are the numbers that matter for the chips that will train and run the next generation of AI models.
The mechanism echoes what Samsung already mastered in memory. V-NAND stacks storage cells vertically. HBM stacks DRAM dies. The company has spent a decade building the manufacturing discipline for vertical integration at scale. Now it is applying that same logic to logic.
The Foundry War's New Axis
Samsung's 42nm gate pitch is a direct assault on the foundry order. The density advantage over Intel's 45nm CFET is real and measured. The advantage over TSMC is harder to quantify, for a simple reason: TSMC has no public CFET demonstration.
Here is the chain of consequences.
Samsung's window. The company targets a prototype logic chip at this 42nm gate pitch by 2027. That timeline puts a working CFET-based chip in Samsung's hands before the decade's end. The density gain is not theoretical. It is a doubling of transistors per unit area compared to planar designs, and a significant leap over current GAAFET nodes. Samsung is now the pace car for the sub-2nm era.
Intel's bind. Intel cannot afford to cede the density narrative. Its foundry ambitions depend on convincing customers—NVIDIA, Qualcomm, Amazon—that its roadmap is credible. A 45nm CFET demo is a proof of life, not a leadership claim. Intel will likely accelerate its CFET timeline. The pressure is not just from Samsung. It is from every hyperscaler designing AI silicon that needs more transistors per watt. If Intel cannot show a path to 40nm or below by mid-2027, the risk is not losing a benchmark. It is losing design wins that lock in for years. Expect a response at IEDM or VLSI next year. The alternative is watching Samsung define the performance benchmarks for AI and HPC chips, the two highest-margin segments in the foundry business.
TSMC's silence. This is now a strategic vulnerability. TSMC dominates the foundry market on the strength of its N3 and N2 nodes, both GAAFET-based. A CFET roadmap leapfrogs GAAFET entirely. TSMC has two options: license CFET intellectual property from Samsung, or pour billions into an internal vertical stacking program that is, by every public indication, years behind. Neither is comfortable. Licensing hands Samsung a recurring revenue stream and a say in how the industry's leading foundry deploys the technology. Going it alone risks arriving late to a market where AI chip designers are already optimizing for Samsung's vertical architecture. If TSMC does not announce a CFET program by its own technology symposium in early 2027, the gap will have widened from a disclosure gap to a competitive one.
The NVIDIA Card
A foundry with a credible CFET offering gives NVIDIA something it has not had in years: a genuine second source for leading-edge logic. Samsung's 2x power efficiency and 100% performance gain claims map directly onto the constraints that limit GPU scaling. Less power per transistor means more transistors per package. More transistors per package means larger models trained in less time.
Samsung's V-NAND and HBM manufacturing experience also means it can offer co-packaged logic and memory in a way that a pure-logic foundry cannot easily replicate. The integration play is as important as the transistor itself. For NVIDIA, which buys both logic wafers and HBM stacks, a single vendor that can optimize both is a procurement and performance advantage. This is the second-order effect that turns a transistor paper into a foundry strategy.
Vertical Experience Is a Moat
The vertical stacking concept was first applied in memory semiconductors, as BusinessKorea notes: V-NAND for NAND flash and HBM for DRAM. Samsung has built fabs, developed etch and deposition processes, and trained engineers around the discipline of building upward rather than outward. That institutional knowledge does not transfer to a competitor by reading a paper.
The 42nm gate pitch is the result of a decade of vertical manufacturing experience that neither Intel nor TSMC possesses. Intel's CFET work is credible but isolated to its research fab. TSMC's is invisible. Samsung is the only firm that can draw on high-volume vertical manufacturing to inform its logic roadmap. That asymmetry will compound as gate pitches shrink further and the tolerances for the intermediate insulating layer tighten.
Planar Scaling Is Over
The 42nm gate pitch is not a number to benchmark. It is the end of a 50-year assumption that transistors spread across silicon. Samsung's Best Paper at VLSI 2026 declares that the next density gains will come from stacking, not shrinking. Intel has a response but not an answer. TSMC has neither.
The foundry race for AI and HPC chips is now a vertical stacking war. Samsung just fired the first shot. It landed on 42 nanometers.
