TSMC will ship its first commercial 2-nanometer chip for a non-Apple customer by Q3 2027. The recipient will be Broadcom, fulfilling orders for a hyperscaler’s custom AI networking ASIC. Apple will still receive N2 silicon, but it will not be the sole launch partner for the first time since the 10-nanometer node.

The Signal Already Exists

TSMC’s N2 process entered risk production in late 2025 with yields above 60 percent on test wafers. That number matters. A node crosses from experimental to commercially viable when defect density drops low enough that a customer can calculate a positive gross margin on finished die. At 60 percent and climbing, the yield curve intersects profitability for high-ASP chips with large reticle limits. Networking ASICs and AI accelerators fit that profile. Smartphone SoCs, with their tighter die size and margin constraints, require yields closer to 80 percent. The physics of defect distribution on gate-all-around nanosheets favors the larger, more redundant designs first. Broadcom confirmed N2 tape-outs on its 2026 earnings call. A tape-out is not a prototype. It is a paid, committed design locked for manufacturing. The only remaining variable is the yield ramp, and the ramp is ahead of schedule.

The Incentive Structure Has Inverted

For a decade, Apple paid a premium to secure the first wafers on every new TSMC node. The arrangement worked because the iPhone’s annual September cadence aligned with TSMC’s summer yield crossover, and Apple’s margins could absorb the defect cost. That calculus breaks at 2 nanometers. The marginal cost of a leading-node wafer has doubled from 5 nanometers to N2. A single N2 wafer now costs north of $30,000. Apple’s iPhone SoC die size, roughly 110 square millimeters, yields fewer than 400 candidates per wafer. At 60 percent yield, the math is punishing. A hyperscaler’s networking ASIC at 400 square millimeters yields fewer than 100 candidates per wafer but sells into a $40,000 system where the chip cost is a rounding error. The buyer does not flinch at wafer pricing. The buyer needs throughput, latency, and power efficiency now, because every watt saved in the switch fabric cascades into cooling and energy savings across a 100,000-node cluster. The hyperscaler’s willingness to absorb low initial yield is not a theory. It is an observed behavior from the 5-nanometer and 4-nanometer ramps, where Amazon’s Trainium and Google’s TPU designs entered production at yield thresholds that would have been unacceptable for a consumer device. At N2, the gap widens further.

The Alternatives Are Structurally Blocked

Samsung’s 2-nanometer gate-all-around process is in development but lacks the logic density and SRAM scaling to compete for high-performance designs. Samsung Foundry lost Qualcomm’s flagship business at 4 nanometers due to yield failures and has not recovered trust for leading-edge orders. Intel’s 18A node is real, but Intel Foundry Services is an unproven manufacturing partner for external customers at scale. A fabless company betting a multi-billion-dollar product line on Intel’s yields would be committing an act of corporate negligence. TSMC holds an effective monopoly on viable 2-nanometer supply for the 2026-2028 window. The only question is which customer’s silicon exits the fab first, and the economics point to the customer with the highest pain threshold on defect density. That customer is not Apple.

The Margin Repricing

When TSMC ships volume N2 wafers to Broadcom before Apple’s iPhone ramp in Q4 2027, the market will be forced to reprice two assumptions. First, that Apple’s process exclusivity is a permanent structural advantage rather than a transient artifact of smartphone economics. Second, that TSMC’s N2 margins will start compressed due to low initial yields. The opposite occurs. Hyperscaler demand for early, low-yield wafers at full price accelerates TSMC’s learning curve and pulls forward the node’s profitability crossover by at least two quarters. TSMC’s gross margin expansion, already underway, receives a tailwind that consensus models have not captured. The company that controls the planet’s most advanced manufacturing process discovers that its pricing power is even greater than previously understood, because the next most demanding customer is no longer a phone maker. It is a data center operator with an insatiable need for bandwidth and a budget that makes a $30,000 wafer look like a line item.

What is driving this

  • TSMC N2 risk production yields crossed 60 percent in late 2025, making high-ASP, large-die chips economically viable before smartphone SoCs.
  • Broadcom confirmed N2 tape-outs in 2026, signaling a committed hyperscaler ASIC design locked for manufacturing.
  • Hyperscaler willingness to absorb low initial yields on networking silicon removes the traditional yield threshold barrier that kept Apple first.
  • Samsung and Intel lack the combined yield maturity and foundry trust to offer a credible alternative 2-nanometer supply before 2028.

What would prove this wrong

TSMC N2 yields stall below 70 percent through mid-2027, making even high-ASP die economically unviable and forcing Broadcom to delay its ramp into 2028.

The signal

TSMC's N2 process reached risk production in late 2025 with yields above 60 percent on test wafers, and Broadcom confirmed N2 tape-outs in its 2026 earnings call.