TSMC will begin volume manufacturing of A16 (1.6 nm) process chips for at least one non-Apple customer by 31 March 2028. This prediction does not rest on a vague sense that technology diffuses faster now. It rests on the specific collapse of Samsung Foundry and Intel Foundry Services as viable alternatives, the physical timeline of Taiwan’s fab construction, and the brute financial logic of a supplier that must recoup sixty billion dollars in annual capital expenditure without letting its margin profile become hostage to a single American design house.

The Supply Deficit Is Now Structural

Samsung’s 1.4 nm node has officially slipped past 2027. Its Gate-All-Around yields at 3 nm remain below fifty percent, and internal priorities have pivoted to memory and advanced packaging for HBM4. Intel’s 14A node, once the centerpiece of its foundry comeback, is now a 2028 risk item after the company halted major fab construction in Magdeburg and trimmed its Ohio timeline. These are not delays. They are vacancies. For any firm that needs to ship a competitive 200-watt AI accelerator or a low-power modem with a sub-4nm gate pitch by 2027, TSMC is the sole source. The physics of EUV lithography and backside power delivery do not permit a shortcut through a second-rate fab. The only question is how TSMC allocates the supply.

Apple’s Exclusivity Was a Market Accident, Not a Policy

Apple has enjoyed a temporary monopoly on the first wave of each new node because it was the only customer willing to buy entire risk-production lots at a premium and co-design its architectures in lockstep with TSMC’s process development. That made sense when the alternative was a commodity Android chipmaker waiting for a price cut. The calculus shifts when the customer demanding early access is Nvidia, whose data center margins on a B200 or an R100 architecture can absorb a premium die cost that makes an iPhone SoC budget look quaint. TSMC’s 2025 to 2026 capex guidance already embeds the tooling for A16 capacity that exceeds Apple’s total wafer demand. The additional cleanroom space in Kaohsiung and Taichung is not being built for a single client. It is being built because hyperscalers and fabless chipmakers have committed to volume orders that require a multi-customer ramp from day one.

The Yield Curve Forces a Parallel Ramp

A16 introduces backside power delivery networks via a buried power rail. This is a genuine physical break from the FinFlex architectures of the N3 and N2 families. It changes thermal behavior, voltage droop, and the entire signoff methodology for physical design. The first tape-outs will be painful. But that pain is precisely why a parallel ramp with a second customer becomes mandatory. TSMC needs high-volume feedback from a non-mobile silicon profile to harden its libraries across thermal densities that Apple’s chips simply do not reach. The incentive is not to gatekeep A16 for a low-power phone processor. The incentive is to use a high-power compute die as an anvil to hammer the process into maturity faster. By late 2027, the risk-production phase will be complete, and the volume curve will inflect. The most aggressive non-Apple partner, likely Nvidia’s “Rubin Next” platform or AMD’s post-MI400 architecture, will hit mass production in time to ship silicon before the March 2028 cutoff.

When this happens, the artificial cadence where Apple enjoys a twelve-to-eighteen-month exclusive on the mobile transistor flagship dissolves. That shifts the upgrade cycle for premium Android devices and, more critically, forces the hyperscale cloud providers to accelerate their ASIC roadmaps. The edge AI device market gets a process node that was supposed to be walled off until 2029. The A16 node becomes a commons, not a walled garden, half a decade faster than the consensus model predicted.

What is driving this

  • Samsung Foundry and Intel Foundry Services have both pushed their sub-2 nm nodes beyond 2028, leaving TSMC as the sole source for advanced logic in the 2027 to 2028 window.
  • TSMC’s A16 capacity investment is sized to produce wafer volumes that exceed Apple’s total node demand, meaning the fab must run a multi-customer queue to hit utilization and margin targets.
  • The backside power delivery architecture of A16 requires high-thermal envelope silicon (data center GPU or AI ASIC) to accelerate the yield learning curve, making a non-Apple partner a technical necessity, not just a commercial one.
  • Nvidia, AMD, and Qualcomm face an existential risk of design irrelevance if they cede a two-year exclusive on the next transistor gate to Apple Silicon, forcing preemptive bidding on risk-production slots.

What would prove this wrong

A catastrophic defect density in the backside power delivery module that pushes A16 volume qualification past June 2028, combined with a total cancellation of the non-Apple risk-production reservations already placed for 2027.

The signal

TSMC’s 2025–2026 capex guidance already earmarks A16 capacity, and Samsung and Intel have publicly delayed their 1.4 nm roadmaps into 2028 or later.