Gallium-doped germanium just made the trillion-dollar CMOS supply chain directly compatible with superconducting qubits.
A single unified map replaces the ocean that once divided two territories.
The material barrier that forced superconducting quantum processors and their classical control logic onto separate, specialized chips is gone. In a paper published in Nature on June 1, 2026, a team from New York University and the University of Queensland report a gallium-doped germanium superconducting semiconductor that interfaces directly with standard CMOS processes. The work, previously detailed in Physical Review Letters on October 14, 2025, and uploaded to arXiv on June 3, 2025, demonstrates Josephson junction arrays, critical current densities, and a clear scaling pathway to tens of millions of qubits per monolithic die. The implication is stark: superconducting qubits and their classical controllers can now be built on the same wafer, using the same fabrication lines that produce billions of transistors for smartphones and servers.
The isolation was physical, not architectural
A new currency flows straight into the counting mechanism, merging minting and measurement in one step.
Superconducting qubits have always been material outcasts. They need millikelvin temperatures to maintain coherence. Classical CMOS logic, while operable at cryogenic temperatures with careful tuning, is designed for 300 K and generates heat and noise that kill qubit stability. For two decades the engineering solution was physical separation: a dilution refrigerator housing the quantum chip, and a rack of room-temperature electronics connected by miles of coaxial cabling. This created a wiring bottleneck that scales quadratically with qubit count. Each additional qubit requires at least two control lines, so a 1,000-qubit processor becomes a plumbing nightmare before it becomes a computational one.
Efforts to move control logic closer to the qubit coalesced around purpose-built cryogenic CMOS (cryo-CMOS) ASICs. Companies such as SEEQC and Quantum Machines built roadmaps around specialized controllers on the 4 K stage—still a separate chip, but close enough to reduce cabling. That architecture assumed a permanent materials divorce: qubit fabrication and CMOS fabrication could not be merged because no superconducting material survived a standard CMOS process without contaminating the line or losing its superconducting properties. Gallium-doped germanium collapses that assumption.
How gallium-doped germanium closes the process gap
Here is what is confirmed from the peer-reviewed record. The Phys. Rev. Lett. paper (133, 136001) describes a full device fabrication flow executed in a CMOS line. The material system is gallium-doped germanium, a group-IV semiconductor that becomes superconducting at cryogenic temperatures while remaining structurally and chemically compatible with the dielectric, metal, and thermal budgets of an advanced CMOS node. The team fabricated Josephson junction arrays directly alongside test structures for classical transistors, using the same lithography, etching, and metallization steps that would build a standard logic gate.
The arXiv preprint from June 2025 provides the technical exposition: process modules for the superconducting layer, doping profiles, annealing conditions, and measured critical current densities that are competitive with aluminum-based junctions. Crucially, it eliminates the interdiffusion and oxidation problems that make aluminum incompatible with CMOS back-end-of-line processing. The work does not just demonstrate a single junction; it demonstrates arrays, the building block of superconducting qubit circuits. And it projects a scaling path to tens of millions of qubits per chip, a density that standalone cryo-CMOS architectures cannot approach because the interposer and cabling parasitics become unmanageable past a few thousand physical qubits.
IBM is not treating this as a lab result. On October 15, 2025, one day after the PRL publication, IBM Research published a blog post authored by members of the team explaining the motivation and implications. Simultaneously, IBM dropped a GitHub repository with PDK-style parameter files, example device layouts, and analysis scripts. That is a design ecosystem signal, not a science communication gesture. A process design kit lets foundry customers simulate, lay out, and tape out circuits. IBM is telling the quantum hardware community: start designing now.
The contrarian take: standalone cryo-CMOS just became a dead end
The consensus reaction will call this a scaling breakthrough for quantum computing. That framing is accurate but incomplete. The far more disruptive, near-term implication is that it threatens the standalone cryo-CMOS controller market before that market fully forms. If the qubit and its classical controller can be fabricated on the same die, with the same process flow, there is no architectural role for a separate cryo-CMOS ASIC. The business case for a specialized 4 K control chip collapses the moment a major foundry offers a monolithic hybrid process.
SEEQC, Quantum Machines, and a handful of venture-backed startups have raised significant capital on the premise that quantum control electronics are a distinct hardware category. They are doing impressive engineering, but they are solving a problem created by a materials incompatibility that this gallium-doped germanium platform eliminates. The Nature paper is a fundamental science result with the commercial side-effect of making an entire architecture category obsolete. A monolithic alternative from a major foundry resets the economics of the entire control stack.
The 24-month foundry call and IBM's pole position
The baseline forecast is that within 24 months a major foundry will announce a multi-project wafer shuttle that includes this gallium-doped germanium material stack. The candidate list is short: TSMC and Samsung are the only logic foundries with the 300 mm capacity, the advanced node experience, and the existing quantum research partnerships needed to industrialize a new material module at scale. IBM, which co-authored the work and already distributes a process design kit for the platform, enters any such partnership as the de facto standard-bearer for hybrid design flows. The PDK on GitHub is a technical asset and simultaneously a strategic move: it defines the design language and simulation environment a foundry must adopt to attract quantum-classical tape-outs, centering IBM's tools and workflows in that adoption loop.
The gold rush will be among quantum hardware startups that currently architect their control systems around off-chip cryo-CMOS. The physics dictates a redesign, not an adaptation. Moving from a separate controller with dedicated interconnects to an on-die co-processor requires rearchitecting the qubit bias network, the readout chain, and the error-correction data path. The teams that move first will be the teams that have been tracking the arXiv preprint since June 2025, have already ported their circuit models to the IBM PDK, and can tape out when the first shuttle runs. The teams that wait for a press release will be catching up on a design cycle that takes 12 to 18 months from tape-out to characterization.
What this means for hardware architects, right now
For a quantum hardware CTO, the immediate action item is to download the IBM PDK from the public repository and start modeling co-integrated qubit and controller circuits. The parameter files map directly to the material properties reported in Phys. Rev. Lett., so simulation fidelity is anchored to published experimental data, not to aspirational targets. The signal to watch is not another journal article. It is a foundry announcement for a multi-project wafer shuttle that includes Ga-doped Ge as a recognized process option. That announcement will appear on the foundry's partner portal before it hits the press. The team with a ready-to-tape-out design when that shuttle opens has a six-month lead on everyone else.
For foundry strategists, the calculus is different. The market pull for monolithic quantum-classical chips is not yet measured in revenue. It is measured in ecosystem lock-in. The foundry that hosts the first successful hybrid tape-out becomes the default platform for a technology that, if the scaling projections hold, will eventually require the most advanced process nodes and the most expensive wafer starts. That is a decade-scale revenue opportunity that starts with a single shuttle run.
The trillion-dollar CMOS supply chain did not adapt to quantum computing. Quantum computing just adapted to the CMOS supply chain.
Gallium-doped germanium makes the qubit a fab-compatible device, and that changes who controls the manufacturing roadmap, who sets the design rules, and who captures the margin. The Nature paper is not the end of this story. It is the starting gun.
